Electronic devices such as memory chips can contain undesired faults and defects that arise due to imperfections in manufacturing processes. These faults and defects include open circuits, short circuits, and out-of-tolerance components. Testing for these faults during manufacture is impractical and costly in light of the new process technologies currently being used to manufacture electronic circuits and devices. Therefore, self-test circuits have been incorporated within modern circuits and devices in order to improve reliability, to eliminate defective and faulty circuits and devices, and to reduce cost.
One example of an incorporated self-test circuit measures the quiescent DC power supply current. This method is referred to as the IDDQ method. In the IDDQ method, power supply currents outside a predetermined range indicate a faulty circuit or device. Examples of this method can be found in U.S. Pat. Nos. 6,342,790, 6,301,168, and 6,144,214. In general, an apparatus incorporating quiescent DC power supply current for self-test monitors the current from a power supply using a current sensor. Therefore, the apparatus effectively monitors the supply current delivered to the Device Under Test (DUT) and transmits a final output signal that is in proportion to the supply current delivered to the DUT. The final output signal is analyzed to determine whether or not any faults exist in the DUT.
The IDDQ method, however, requires quiescent defect currents of appreciable magnitude relative to the quiescent currents in fault-free circuits and devices. But the difference between faulty currents and fault-free currents may be negligible in many components. Moreover, quiescent leakage currents associated with emerging technologies are large enough to render these IDDQ methods ineffective in detecting faulty circuits.
These emerging technologies include deep sub-micron integrated circuit technology. Sub-micron circuits have increased leakage currents and associated large DC supply currents that greatly reduce the effectiveness of the IDDQ methods. Additional challenges to testing of sub-micron circuits include significant increases in circuit size, rapid increases in clock frequencies, the dominance of the interconnect delay, the transmission-line behavior of interconnects, the reduced level of the power supply voltage, the increase in leakage currents, the increase in power consumption, and the increased sensitivity of circuit arrangements to process defects. Therefore, fault monitoring circuitry was developed for measurement of the transient power supply current. Methods employing such circuitry are referred to as IDDT methods wherein transient power supply currents outside a predetermined range indicate a faulty circuit or device.
U.S. Pat. No. 6,414,511 discloses an example of an IDDT method. In general, an apparatus incorporating transient power supply current for self-test monitors the current from the power supply using a current sensor. Therefore, the apparatus effectively monitors the transient supply current delivered to the Device Under Test (DUT) and transmits a final output signal that is in proportion to the transient supply current of the DUT. The final output signal is analyzed to determine whether or not any faults exist in the DUT.
Prior implementations of the IDDT methods, however, do not adequately address the need for large bandwidths to handle the extremely short duration underlying transients in deep sub-micron technology. These prior methods have relied on dubious and inadvertent integration of the high-speed transients (i.e., lowpass filtering of transients) to allow slower circuits to process the transients. In such methods, the extremely high-speed transients native to the DUT are the transients being observed and measured for the purpose of detecting faulty circuits. The associated high-speed transients have led to over-simplified and questionable solutions, which have not found application in industry. Moreover, the bandwidth of such transients in digital circuits are by their very nature faster than the highest clock speeds of the circuit, since the duration of the transient is commonly shorter than the logic rise and fall times.
Therefore, a need exists to find alternative methods and apparatus that effectively and practically utilize transient power supply currents in testing devices and circuits for faults and defects. Suitable methods and apparatus should be capable of testing with little disruption of the circuits under test, with little added hardware, and with minimal effect on manufacturing costs. In addition, suitable methods and apparatus should be capable of the necessary testing at lower speeds and bandwidths to be advantageous for implementations in circuits, devices, and systems.